EPM7032AE Demo

Here's the code I use to test all the CPLD boards before they get packaged and shipped out.

The code tests all IO pins of the CPLD and one of the clock pins.

The output of each [number] pin is connected physically connected to the corresponding input [number] pin using a prototype vero board. So, IN[0] is physically connected to OUT[0].... and IN[7] is physically connected to OUT[7], and so on.

This allows the real value of OUT[x] to be read by IN[x].

At every positive clock edge that value of all the input pins are read and copied to the next number output pin. eg IN[3] -> OUT[4]. This is done for all pins except OUT[0] is set to be the opposite state of IN[13]. This creates a cool 'light chaser affect'.

If there is an issue with a pin (short or open circuit) the light chaser effect will not work properly, and the problem pin(s) can be easily identified and corrected.

For the clock source I have programmed an Atmel ATtiny85 to quickly toggle one of it's pins on and off.

module brdtester(IN, OUT, CLK); input CLK; input [13:0]IN; output [13:0]OUT; reg [13:0]OUT; initial begin OUT[0] = 1; OUT[1] = 0; OUT[2] = 0; OUT[3] = 0; OUT[4] = 0; OUT[5] = 0; OUT[6] = 0; OUT[7] = 0; OUT[8] = 0; OUT[9] = 0; OUT[10] = 0; OUT[11] = 0; OUT[12] = 0; OUT[13] = 0; end always@(posedge CLK) begin OUT[13] = IN[12]; OUT[12] = IN[11]; OUT[11] = IN[10]; OUT[10] = IN[9]; OUT[9] = IN[8]; OUT[8] = IN[7]; OUT[7] = IN[6]; OUT[6] = IN[5]; OUT[5] = IN[4]; OUT[4] = IN[3]; OUT[3] = IN[2]; OUT[2] = IN[1]; OUT[1] = IN[0]; OUT[0] = !IN[13]; end endmodule

Pin NodePIN_40 CLKPIN_3 IN[0]PIN_6 IN[1]PIN_31 IN[10]PIN_34 IN[11]PIN_42 IN[12]PIN_44 IN[13]PIN_10 IN[2]PIN_12 IN[3]PIN_14 IN[4]PIN_18 IN[5]PIN_20 IN[6]PIN_22 IN[7]PIN_25 IN[8]PIN_28 IN[9]PIN_2 OUT[0]PIN_5 OUT[1]PIN_30 OUT[10]PIN_33 OUT[11]PIN_35 OUT[12]PIN_43 OUT[13]PIN_8 OUT[2]PIN_11 OUT[3]PIN_13 OUT[4]PIN_15 OUT[5]PIN_19 OUT[6]PIN_21 OUT[7]PIN_23 OUT[8]PIN_27 OUT[9]